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handle initial connection, diggital trigger

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This commit is contained in:
wendtalexander 2024-09-26 11:24:03 +02:00
parent 1dc72d00bb
commit d3800ddfa2
1 changed files with 11 additions and 6 deletions
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17
pyrelacs/repros/mccdac.py
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@ -19,7 +19,11 @@ class MccDac:
log.error("Did not found daq devices, please connect one")
exit(1)
self.daq_device = uldaq.DaqDevice(devices[0])
self.daq_device.connect()
try:
self.daq_device.connect()
except uldaq.ul_exception.ULException:
self.disconnect_dac()
self.connect_dac()
self.ai_device = self.daq_device.get_ai_device()
self.ao_device = self.daq_device.get_ao_device()
self.dio_device = self.daq_device.get_dio_device()
@ -85,8 +89,8 @@ class MccDac:
buffer = c_double * len(data)
data_analog_output = buffer(*data)
log.debug(f"Created C_double data {data_analog_output}")
try:
err = self.ao_device.a_out_scan(
channels[0],
@ -123,12 +127,13 @@ class MccDac:
self.disconnect_dac()
def diggital_trigger(self) -> None:
if not self.read_bit(channel=0):
self.write_bit(channel=0, bit=1)
else:
data = self.read_bit(channel=0)
if data:
self.write_bit(channel=0, bit=0)
time.time_ns()
self.write_bit(channel=0, bit=1)
else:
self.write_bit(channel=0, bit=1)
def write_bit(self, channel: int = 0, bit: int = 1) -> None:
self.dio_device.d_config_bit(
@ -266,7 +271,7 @@ class MccDac:
log.info("Muting channel one")
binary_db2 = "00000000"
channels_db = binary_db1 + binary_db2
channels_db = binary_db2 + binary_db1
self.write_bit(channel=4, bit=0)
for b in channels_db:
self.write_bit(channel=5, bit=int(b))