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trying to fix seg fault

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This commit is contained in:
wendtalexander 2024-09-25 15:31:15 +02:00
parent deb60fa84c
commit 1a2185d5e4
2 changed files with 21 additions and 20 deletions
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4
pyrelacs/repros/calbi.py
View File

@ -50,12 +50,12 @@ class Calibration(MccDac):
# sending stimulus
log.debug(f"{data}, {data.shape}")
embed()
exit()
# self.set_attenuation_level(db_channel1=0.0, db_channel2=0.0)
# self.set_analog_to_zero()
# time.sleep(1)
log.debug(self.ao_device)
embed()
exit()
self.write_analog(
data,

13
pyrelacs/repros/mccdac.py
View File

@ -95,7 +95,7 @@ class MccDac:
log.debug(f"Created C_double data {data_analog_output}")
log.info(self.ao_device)
try:
err = self.ao_device.a_out_scan(
channels[0],
channels[1],
@ -108,10 +108,10 @@ class MccDac:
)
# self.diggital_trigger()
# self.ao_device.scan_wait(uldaq.WaitType.WAIT_UNTIL_DONE, 11)
except Exception as e:
print(f"{e}")
self.set_analog_to_zero()
self.disconnect_dac()
# except Exception as e:
# print(f"{e}")
# self.set_analog_to_zero()
# self.disconnect_dac()
def set_analog_to_zero(self, channels: list[int] = [0, 1]):
try:
@ -132,11 +132,12 @@ class MccDac:
def diggital_trigger(self, channel: int = 0) -> None:
bit_channel = self.read_bit(channel)
log.debug(bit_channel)
if not bit_channel:
self.write_bit(channel, 1)
else:
self.write_bit(channel, 0)
time.time_ns()
time.sleep(1)
self.write_bit(channel, 1)
def write_bit(self, channel: int = 0, bit: int = 1) -> None: